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Semiconductor R&D and design

From scientific evidence toward open silicon.

Connect literature, patents, materials, lithography, metrology, experiments, device physics, circuits, RTL, verification, and public-PDK implementation in one traceable workspace.

Evidence intake

Experiment planning

RTL architecture and verification

4 × 4 systolic array · real managed synthesis
Isometric 4 by 4 systolic array with signed INT8 activations and weights

Example study

From “tiny AI engine” to a real synthesized hierarchy.

This study is understandable at a glance—numbers flow through a grid—but it exercises the disciplines that make open chip design real: interfaces, signed arithmetic, accumulation width, reset, timing of data movement, lint, synthesis, provenance, and honest implementation boundaries.

16

Parallel processing elements

A retained 4 × 4 systolic hierarchy

16 MAC/cycle

Peak architectural parallelism

After the wavefront fills the array

64 / 64

Reference outputs matched

Independent cycle model versus integer reference

12,961

Generic Yosys cells

937 sequential and 12,024 combinational

01

Design brief

Start with a recognizable chip idea

The brief is a tiny AI inference engine: multiply two signed 4 × 4 integer matrices while many small processing elements work in parallel.

02

Architecture

Design the data movement

Signed INT8 activations move horizontally, signed INT8 weights move vertically, and each processing element accumulates into a 24-bit result.

03

Numerical model

Make the wavefront visible

A cycle model shows 64 multiply–accumulate operations sweeping diagonally across the array and checks four matrices against an integer reference.

04

Targeted correction

Let the guardrail find a real defect

The first managed lint stopped on two redundant unsigned comparisons. Vicena preserved the failure, removed only those comparisons, and kept the architecture unchanged.

05

Managed compute

Synthesize the corrected RTL

Verilator 5.032 passed lint, Yosys 0.52 reported zero check problems, and the managed netlist retained all 16 named processing-element instances.

06

Design evidence

Inspect what was actually built

The hierarchy, netlist, generic logic-cell composition, checksums, scorecard, and exact job provenance remain available for review and the next implementation stage.

Real workflow artifacts

Architecture, behavior, and netlist tell the same story.

The notebook begins with the human model of the chip, makes the parallel wavefront visible, checks the arithmetic reference, and finishes with figures parsed from the managed Yosys netlist.

Traceable outputs
Isometric architecture diagram of a 4 by 4 signed INT8 systolic matrix multiplier

A tiny AI engine made of 16 cooperating processors

Activations and weights enter along different axes. Every processing element performs signed 8 × 8 multiply–accumulate work and retains a 24-bit result.

Cycle-by-cycle wavefront timing of 64 multiply accumulate operations across 16 processing elements

The computation moves like a wave

The timing map makes concurrency concrete: four inner products traverse each row and column while the active diagonal advances across the array.

Zero-error heatmaps for four independent systolic-array cycle-model reference comparisons

Every cycle-model result matched

Four matrix cases—including signed extremes—produced 64 exact matches against the integer reference. This is cycle-model evidence, not RTL simulation.

Managed Yosys netlist hierarchy retaining 16 processing elements

The managed netlist retained the array

The real netlist contains a top controller, result bus, and 16 hierarchical systolic_pe_8x24 instances rather than a flattened conceptual drawing.

Actual technology-independent Yosys cell composition and architectural scaling chart

Actual synthesized logic composition

The chart is parsed from managed netlist.json: 12,961 technology-independent cells, split into 937 sequential and 12,024 combinational cells.

Managed synthesis scorecard for a 4 by 4 signed INT8 systolic array

One scorecard connects intent to evidence

Architecture, arithmetic width, reset behavior, numerical reference, lint, synthesis, hierarchy, cell counts, job ID, and scientific boundaries stay together.

Connected R&D workflows

Research questions, process evidence, and design artifacts stay connected.

Semiconductor development spans more than RTL. Vicena can keep lithography, metrology, defects, materials, experiments, device physics, circuits, and chip implementation connected without overstating what any one workflow proves.

EUV process landscape with CD contour, defect risk, uncertainty, measured DOE, and next-test markers

Lithography process development

Analyze focus-exposure matrices, Bossung curves, process windows, CD response, stochastic variability, and next DOE points.

Wafer signature decomposition showing measured map, radial trend, residual field, and radial profile

Wafer-map and metrology analytics

Decompose wafer-level signatures into radial trends, residuals, field effects, outliers, CDU, overlay, film thickness, and defect distributions.

Defect morphology embedding map with clustered semiconductor defect signatures

Defect and failure analysis

Cluster defect morphologies, connect process changes to failure hypotheses, and produce targeted next-test plans for review.

Materials tradeoff map showing process performance, compatibility margin, evidence, and Pareto candidates

Materials and process chemistry

Screen candidates for compatibility, residue risk, outgassing concern, solubility, hazards, process performance, and supporting evidence.

Aerial image, resist contour, profile, and edge-slope visualization

Aerial image and resist contour modeling

Explore how pattern geometry, source assumptions, threshold behavior, printed contours, and edge slope affect lithography decisions.

Stochastic line-edge ensemble, CD distribution, and robustness analysis for semiconductor lithography

Stochastic variability and robustness

Visualize line-edge ensembles, CD distributions, process uncertainty, and robustness against focus, dose, and material variation.

Scientific packages

The scientific packages behind digital, physical, and device design.

  1. Icarus Verilog

    12

    RTL simulation

    Compiles Verilog and SystemVerilog testbenches, executes them with vvp, and produces inspectable VCD waveforms.

  2. Verilator

    5.032

    SystemVerilog lint

    Finds syntax, width, signedness, unreachable logic, and other RTL problems before synthesis or implementation.

  3. Yosys

    0.52

    Logic synthesis

    Transforms RTL into technology-independent netlists and reports hierarchy, cells, memories, and structural checks.

  4. OpenROAD

    public 26Q3 workbench

    RTL-to-GDS physical design

    Carries suitable designs through floorplanning, placement, clock-tree synthesis, routing, timing, and public-PDK implementation.

  5. KLayout

    Layout and GDS inspection

    Generates and inspects GDS layouts and supports physical-verification work around public semiconductor platforms.

  6. DEVSIM

    2.10

    Semiconductor-device simulation

    Solves drift-diffusion and related device equations for diodes, transistors, materials, contacts, and electrical characteristics.

Scientific capabilities

A path from algorithms toward open silicon.

Vicena can connect multiple open-source design layers while keeping their claims separate: mathematical reference, RTL behavior, logic synthesis, device physics, circuits, and physical implementation.

Evidence intake

Turn early technical questions into cited literature briefs, patent landscapes, material comparisons, and open-question lists.

Experiment planning

Convert evidence and hypotheses into DOE tables, metrology plans, controls, acceptance criteria, and next-test recommendations.

RTL architecture and verification

Develop Verilog designs, explicit interfaces, reset behavior, pipelines, test strategies, lint checks, and numerical references.

Notebook execution

Use reproducible notebooks for process windows, wafer maps, defect metrics, surrogate models, and data analysis that can be inspected later.

Decision artifacts

Generate technical briefs, CSV tables, figures, notebooks, compatibility memos, method drafts, and review-ready reports.

Open-source logic synthesis

Use managed Verilator and Yosys workflows to inspect warnings, hierarchy, netlists, generic cells, and synthesis checks.

Public-PDK implementation

Extend suitable designs toward OpenROAD-based floorplanning, placement, routing, timing, DRC/LVS, and reproducible RTL-to-GDS studies.

Device and power-electronics research

Connect DEVSIM device models, ngspice circuits, control electronics, and open semiconductor workflows without conflating their evidence levels.

Evidence discipline

The correction is part of the record.

Production-quality design is not the absence of warnings. It is the ability to stop on a real issue, change only what the evidence supports, and preserve the successful and failed artifacts needed to audit the decision.

The successful managed synthesis is Vicena job lca3fe665ef84a8617eb71ce8b3b61df0f.
Verilator 5.032 passed lint; Yosys 0.52 (fee39a3284c90249e1d9684cf6944ffbbcbb8f90) completed with zero check problems.
Managed netlist.json and netlist.v were retrieved with recorded SHA-256 checksums.
The first lint failure remains in provenance, and the final notebook identifies the exact two-line correction rather than erasing the iteration.

Scientific boundary

Synthesized RTL is not a manufactured chip.

! The 64 exact matches come from an independent Python cycle model, not a managed RTL simulation or formal-equivalence proof.
! The reported cells are technology-independent Yosys logic cells, not characterized standard-cell area.
! No open PDK, Liberty timing library, floorplan, placement, routing, extraction, static timing analysis, DRC/LVS, or power analysis was used.
! This study makes no claim about clock frequency, timing closure, power, physical area, manufacturability, silicon yield, or tapeout readiness.

Start with your design

What should your next open chip do?

Describe the behavior and constraints. Vicena can structure the design, choose the appropriate open workflow, and keep every verification layer visible.